Switch Port Aggregation with EtherChannel
As discussed in Affiliate 3, “Basic Switch and Port Configuration,” switches can use Ethernet,
Fast Ethernet, or Gigabit Ethernet ports to calibration articulation speeds by a agency of ten. Cisco offers
another adjustment of ascent articulation bandwidth by accumulation or bundling alongside links, termed the
EtherChannel technology. Two to eight links of either Fast Ethernet (FE) or Gigabit Ethernet (GE)
are arranged as one analytic articulation of Fast EtherChannel (FEC) or Gigabit EtherChannel (GEC),
respectively. This array provides a full-duplex bandwidth of up to 1600 Mbps (8 links of Fast
Ethernet) or 16 Gbps (8 links of Gigabit Ethernet).
As the Spanning-Tree Protocol (STP) allocation of this affiliate discusses, switches should never
be configured to accept assorted links affiliated to anatomy a loop. EtherChannel avoids this
situation by bundling alongside links into a distinct analytic link, which can act as either an access
or a block link. Switches or accessories on anniversary end of the EtherChannel articulation charge accept and
use the EtherChannel technology for able operation.
Although an EtherChannel articulation is apparent as a distinct analytic link, the articulation does not accept an inherent
total bandwidth according to the sum of its basic concrete links. For example, accept a FEC
link is fabricated up of four full-duplex 100-Mbps Fast Ethernet links. Although it is accessible for the
FEC articulation to backpack a throughput of 800 Mbps, the distinct consistent FEC articulation does not accomplish at
this speed. Instead, cartage is counterbalanced beyond the alone links aural the EtherChannel. Each
of these links operates at its inherent acceleration (200 Mbps full-duplex for FE) but carries alone the
frames placed on it by the EtherChannel hardware. The load-balancing action is explained
further in the abutting section.
EtherChannel additionally provides back-up through the use of the several arranged concrete links.
If one of the links in the array fails, cartage beatific through that articulation will move to an adjoining link.
Failover occurs in beneath than a few milliseconds and is cellophane to the end user. As added links
fail, added cartage will be confused to added adjoining links. Likewise, as links are restored, the load
will be redistributed amid the links