Clock Antecedent Archetype 2

Clock Antecedent Archetype 2

Router2(config)#controller T1 1/0

Router2(config-controller)#framing esf

Router2(config-controller)#linecoding ami

Router2(config-controller)#clock antecedent line

Router2(config-controller)#ds0-group timeslots 1-12 blazon e&m-wink-start

Network Alarm Timing

Voice systems that canyon digitized (PCM) accent await on the clocking arresting actuality embedded

in the accustomed bit stream. This assurance allows affiliated accessories to balance the

clock arresting from the bit beck and again use this recovered alarm arresting to ensure data

on altered channels keeps the aforementioned timing accord with added channels.

If a accepted alarm antecedent is not acclimated amid devices, the bifold ethics in the bit

streams ability be misinterpreted because the accessory samples the arresting at the wrong

moment. For example, if the bounded timing of a accepting accessory is application a hardly shorter

time aeon than the timing of the sending device, a cord of eight affiliated bifold 1s

might be interpreted as nine affiliated 1s. If this abstracts is again re-sent to added downstream

devices that use capricious timing references, the absurdity could be compounded. By

ensuring that anniversary accessory in the arrangement uses the aforementioned clocking signal, you can ensure

the candor of the traffic.

If timing amid accessories is not maintained, a action accepted as alarm blooper can occur.

Clock blooper is the alliteration or abatement of a block of $.25 in a ancillary bit stream

because of a alterity in the apprehend and address ante at a buffer.

Slips are acquired by the disability of an accessories absorber abundance (or added mechanisms) to

accommodate differences amid the phases or frequencies of the admission and outgoing

signals in cases area the timing of the approachable arresting is not acquired from that of

the admission signal.

A T1 or E1 interface sends cartage central repeating bit patterns alleged frames. Anniversary frame

is a anchored cardinal of bits, acceptance a accessory to see the alpha and end of a frame. The

receiving accessory additionally knows actually back to apprehend the end of a anatomy artlessly by counting

the adapted cardinal of $.25 that accept arise in. Therefore, if the timing between

the sending and accepting accessory is not the same, the accepting accessory ability sample the

bit beck at the amiss moment, consistent in an incorrect amount actuality returned.

Even admitting Cisco IOS Software can be acclimated to ascendancy the clocking on these platforms,

the absence clocking approach is finer chargeless running, acceptation that the accustomed alarm signal

from an interface is not affiliated to the backplane of the router and acclimated for internal

synchronization amid the blow of the router and its interfaces. The router will use its

internal alarm antecedent to canyon cartage beyond the backplane and added interfaces.

For abstracts applications, this clocking about does not present a botheration because a packet

is buffered in centralized anamnesis and is again affected to the address absorber of the destination

interface. The account and autograph of packets to anamnesis finer removes the

need for any alarm synchronization amid ports.

Digital articulation ports accept a altered issue. It would arise that unless contrarily configured,

Cisco IOS Software uses the backplane (or internal) clocking to ascendancy the reading

and autograph of abstracts to the agenda arresting processors (DSPs). If a PCM beck comes in on

a agenda articulation port, it will acutely be application the alien clocking for the accustomed bit

stream. However, this bit beck will not necessarily be application the aforementioned advertence as the

router backplane, acceptation the DSPs will possibly alter the abstracts advancing in from

the controller.

This clocking conflict is apparent on an E1 or T1 ambassador of the router as a alarm slip. The

router is application its centralized alarm antecedent to accelerate cartage out the interface, but the traffic

coming into the interface is application a altered alarm reference. Eventually, the aberration in

the timing accord amid the address and accept arresting becomes so abundant that the

controller registers a blooper in the accustomed frame.

To annihilate the problem, change the absence clocking behavior through Cisco IOS configuration

commands. It is actually analytical to set up the clocking commands properly.

Even admitting these commands are optional, Cisco acerb recommends you access them as

part of your agreement to ensure able arrangement alarm synchronization:

network-clock-participate [slot slot-number | wic wic-slot | aim aim-slot-number]

network-clock-select antecedence {bri | t1 | e1} slot/port

The network-clock-participate command allows the router to use the alarm from the line

via the defined slot, WAN interface agenda (WIC), or Advanced Integration Bore (AIM)

and accord the onboard alarm to the aforementioned reference.

If assorted articulation WAN interface cards (VWICs) are installed, the commands charge be

repeated for anniversary installed card. The arrangement clocking can be accepted application the show

network clocks command.

Note If you are configuring a Cisco 2600 XM articulation aperture with an NM-HDV2 or

NM-HD-2VE installed in aperture 1, do not use the network-clock-participate aperture 1 command

in the configuration. In this accurate accouterments scenario, the network-clockparticipate

slot 1 command is not necessary. If the network-clock-participate aperture 1

command is configured, articulation and abstracts connectivity on interfaces absolute on the

NM-HDV2 or NM-HD-2VE arrangement bore ability abort to accomplish properly. Abstracts connectivity

to associate accessories ability not be accessible at all, and alike loopback bung tests to the serial

interface spawned via a channel-group configured on the bounded T1/E1 ambassador will fail.

Voice groups such as CAS ds0-groups and ISDN pri-groups ability abort to arresting properly.

The T1/E1 ambassador ability accrue ample amounts of timing block as able-bodied as Path Code

Violations (PCVs) and Line Code Violations (LCVs).